The present invention relates to a technique which is especially useful when applied to a semiconductor device having a plurality of IIL (i.e., Integrated Injection Logic) elements and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device having a logic circuit composed of IIL elements and an analog circuit composed of bipolar transistors.
An IIL element is characterized by a high integration density and a low power consumption. Such an IIL element is produced at a low cost because it can be formed on a substrate by using a similar process to that of fabricating bipolar transistors used in an analog circuit. Therefore, an inexpensive semiconductor device having a logic circuit composed of IIL elements and an analog circuit composed of bipolar transistors has been widely adopted in an IC (i.e., integrated circuit) for public and industrial applications.
The operation speed of the IIL element has been remarkably improved to have a high speed by the recent progress of techniques related to VLSI (i.e., Very Large-Scale Integration) processes and devices. Therefore, the IIL element has been noted as a fundamental circuit for future VLSI.
On the other hand, a wiring method of electrically wiring between semiconductor elements has also been noted in accordance with the recent minute structure of semiconductor elements. This is because the minute structure never fails to promote a higher wiring density.
This high wiring density can be achieved to some extent by adopting a multi-layered wiring structure. Despite of this fact, however, the adoption has to be determined while sufficiently considering how to use the multi-layered wiring layer. If wirings are formed by randomly using the multi-layered wiring layers without determining the usage, the wiring density may sometimes be decreased. This is because the wirings have to be spaced so that they may be prevented from being shorted. Moreover, the drop in the wiring density raises another problem that the integration density of the device itself is also dropped. In the fabrication of the IC composed of highly densified semiconductor elements, therefore, the method of using the multi-layered wirings is considered to become an important target in future.
In the recent design of ICs, on the other hand, the computer-aided design (i.e., CAD) technique for designing the wires between semiconductor elements by using a computer advances to promote shortening of the IC design time.